1. Field of the Invention
The present invention relates generally to the field of semiconductor device fabrication and, more particularly, to interposers and semiconductor die substrates including slanted or sloped vias formed therethrough and methods for their fabrication. The present invention additionally relates to spring-like deflecting contacts and methods for their fabrication.
2. State of the Art
In order to function, integrated circuits such as semiconductor dice must be in electrical communication with signal inputs and outputs as well as power and ground or bias connections external to the integrated circuit. For example, power and ground or other reference voltage must be supplied for operation of the integrated circuit, and other connections, such as for input, output and timing signals, may also be required. These connections are conventionally made through leads or other conductive elements connected to bond pads present on the active surface of a semiconductor die. However, an inner lead bond (ILB) pattern on the active surface of a semiconductor die may include contacts in the form of bond pads which are very small, i.e., 100 microns square, very closely spaced or pitched (typically along or adjacent a center line of the die or along a periphery of the die) and, as a result, are difficult to align with and electrically contact because of their relatively small size.
To electrically connect to the small contacts in the ILB pattern, the contacts in the form of bond pads of the ILB pattern may be redistributed to other locations on the active surface using a redistribution layer (RDL). The RDL comprises a plurality of conductive traces extending from the bond pads of the ILB pattern to redistribute the contact locations of the ILB pattern to another I/O terminal layout, such as an outer lead bond (OLB) pattern that includes terminal pads, which are more widely pitched and, thus, easier to electrically contact.
Where present, the traces of an RDL may be embedded into a dielectric material. Suitable dielectric materials may include benzocyclobutene (BCB), polyimide, and photosensitive dielectrics. The process steps depend on whether the redistribution traces are aluminum or copper. For aluminum traces, the aluminum is sputtered onto the wafer surface and the traces are etched using a photolithography-defined etch mask pattern comprising a resist. In the case of copper traces, the metal is electroplated onto the wafer surface and then selectively etched to form traces. An RDL may conventionally be applied on the active surface of a semiconductor die to enable flip-chip mounting of the resulting “chip-scale” package on a carrier substrate such as an interposer or a printed circuit board. However, the formation of the RDL traces and redistributed contact pads requires at least one extra step in the fabrication process of a semiconductor die and adds time and expense to the fabrication process.
Another method of providing external electrical contacts to integrated circuitry of a semiconductor die is to form vias, or through-holes, extending between the active surface and the back side of the semiconductor die (typically while the die is at the wafer level and in conjunction with the formation of vias in all of the semiconductor dice of the wafer or other bulk substrate) and to fill the vias with a conductive material. However, one problem of conventionally providing vias through semiconductor dice from an ILB pattern is that the size and pitch of the bond pads have been continually decreasing while the total number of bond pads on a single semiconductor die has been continually increasing due to ongoing advances in semiconductor fabrication and increased circuit complexity. For example, a chip scale package can include a hundred or more external contacts, each having a lateral extent of about 10 mils and a pitch of about 30 mils. While it is possible to reroute the ILB pattern on the active surface of a semiconductor die and then form vias through the semiconductor die substrate from redistributed contact locations to the back side thereof, such an approach is self-defeating as still requiring an RDL extending to the via locations. Further, there may not be sufficient space, or “real estate,” on the active surface to provide sufficient redistributed locations for vias, which are also sometimes known as “through wafer interconnects,” or “TWIs.”
A technique for reducing the real estate required on a carrier substrate is the use of stacked semiconductor chips in a single package. In stacked chip-scale packages, two or more semiconductor chips will be mounted in a stack and electrically interconnected to a carrier substrate and/or to one another. This reduces the space taken on the underlying carrier substrate in comparison to mounting separate chips directly to the substrate.
Stacked chip-scale packages may require vias to be formed through the entire thickness of a semiconductor die between the active surface and backside thereof, allowing electrical connection therethrough to one or more dice stacked thereon. Conventionally, such vias are filled with conductive material to interconnect electrical devices and metallization at various levels.
Electrical contact structures are an integral part of connecting semiconductor devices to external electrical components, such as other semiconductor devices, printed circuit boards, probe cards, etc. There are several conventional bonding methods known in the art for electrically connecting semiconductor devices to another electrical device. Some of these methods include wire bonding, tab bonding, solder-bump bonding, and flip-chip bonding, among many other methods.
Another example of electrical contacts is described in U.S. Pat. No. 5,848,685 to Smith et al. (“the Smith Patent”) entitled “Photolithographically Patterned Spring Contact,” the disclosure of which is incorporated by reference herein and the article “Nanosprings—New Dimensions in Sputtering” available on the worldwide web at semiconductors.unaxis.com/en/p44—47_nanosprings.pdf. The above documents disclose photolithographically patterned spring contacts that may be used for flip-chip contacts or for probe card applications. FIG. 12 is a side view of such a spring contact. Bonding structure 100 includes a plurality of spring contacts 34. Each spring contact 34 comprises a free, cantilevered portion 42 and an anchor portion 46 fixed to an insulating underlayer 48 made from silicon nitride or other etchable insulating material and electrically connected to a contact pad 50. Each spring contact 34 is made of an extremely elastic material, such as a chrome-molybdenum alloy or a nickel-zirconium alloy. The contact pad 50 is the terminal end of a line or trace that electrically communicates between an electronic device formed on the substrate 44 or device 101 such as a transistor, a display electrode, or other electrical device. However, while the patterned spring contacts of the Smith Patent may be used to create an array of spring contacts connectable to an external device, the method of forming them requires a series of complex steps.
Accordingly, a need exists for a via that efficiently facilitates connection between the fine pitch bond pads of an ILB pattern and external electrical devices, and a spring contact that is easy to manufacture.